1. Field of Invention
This invention relates to a semiconductor device package and, more particularly, to a package which is configured to reliably connect an integrated circuit (i.e., chip) to a substrate using encapsulant injected between connection areas which couple the chip to the substrate and further along lateral surfaces of an integrated circuit.
2. Description of Related Art
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit is typically secured within a protective semiconductor device package. Each I/O pad of the chip is then connected to one or more terminals of the device package. The terminals of a device packages are typically arranged about the periphery of the package. Fine metal wires are typically used to connect the I/O pads of the chip to the terminals of the device package. Some types of device packages have terminals called "pins" for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called "leads" for attachment to flat metal contact regions on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. Mishandling can result in a loss of lead coplanarity, adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Controlled collapse chip connection (C4) is a well known method of attaching an integrated circuit chip directly to a PCB, and is commonly referred to as the "flip chip" method. In preparation for C4 attachment, the I/O pads of the chip are typically arranged in a two-dimensional array upon an underside of the chip, and a corresponding set of bonding pads are formed upon an upper surface of the PCB. A solder "bump" or "ball" is formed upon each of the I/O pads of the chip. During C4 attachment of the chip to the PCB, the solder balls are placed in physical contact with the bonding pads of the PCB. The solder balls are then heated long enough for the solder to flow. When the solder cools, the I/O pads of the chip are electrically and mechanically coupled to the bonding pads of the PCB.
Due to the fact that the silicon of the chip expands at a lower rate than the fiberglass-epoxy laminate of the PCB, the solder balls are subjected to mechanical forces during temperature cycling and eventually fail. As a result, the reliabilities of flip chip solder ball connections are relatively low. This problem of thermomechanical mismatch between the silicon chip and the fiberglass-epoxy laminate PCB is typically solved by filling the region between the chip and the PCB with a liquid polymer adhesive "underfill" material which becomes substantially rigid (i.e., hardens) with curing (e.g., time, temperature, etc.). Once cured, the underfill material essentially interlocks the surfaces of the chip and the PCB surrounding the solder balls, reducing the mechanical forces acting upon the solder balls during temperature cycling. In addition, the underfill material encapsulates the C4 connections, protecting them from contaminants (e.g., moisture, electrically conductive particles, etc.) As a result, the reliabilities of the solder ball connections are substantially increased.
Following solder ball reflow during the C4 process, the underfill material is typically dispensed along one or two sides of the chip. Capillary action is commonly relied upon to draw the liquid underfill material into the region between the chip and the PCB. The PCB and attached chip are typically heated to lower the viscosity of the liquid underfill material, facilitating the dispensing of the underfill material. The PCB may also be tilted at an angle such that the force of gravity helps pull the underfill material into the region between the chip and the PCB.
Although relatively simple, the methods currently relied upon to dispense underfill material have disadvantages. In order to substantially fill the region between the chip and the PCB, the viscosity of the underfill material should be within a certain range. Relying upon capillary action and gravity, the underfill process takes time. Despite close process controls, voids sometimes occur within the underfill material which jeopardize the reliabilities of adjacent solder ball connections. The interlocking of the surfaces of the chip and the PCB surrounding the solder balls by the underfill material relies solely upon the adhesion of the underfill material to surfaces of the PCB and the chip.
Like flip chips, grid array semiconductor device packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (BGA) device package. A BGA device includes a chip mounted upon a larger substrate made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, Al.sub.2 O.sub.3, or aluminum nitride, AlN). The substrate includes two sets of bonding pads: a first set adjacent to the chip and a second set arranged in a two-dimensional array across the underside surface of the device package. Members of the second set of bonding pads function as device package terminals, and are coated with solder. The resulting solder balls on the underside of the BGA device package allow the device to be surface mounted upon an ordinary PCB. The I/O pads of the chip are typically connected to corresponding members of the first set of bonding pads by signal lines (e.g., fine metal wires). The substrate includes one or more layers of signal lines (i.e., interconnects) which connect respective members of the first and second sets of bonding pads. During PCB assembly, the BGA device package is attached to the PCB by reflow of the solder balls just as a flip chip is attached to a PCB.
It would be beneficial to have a system and method for packaging an integrated circuit device, wherein the chip is mounted upon a substrate of a grid array semiconductor device package using the C4 or flip chip attachment method, and wherein the underfill material is dispensed by injection. The use of C4 attachment would reduce many of the problems associated with using fine metal wires to connect the I/O pads of the chip to corresponding bonding pads of the BGA package, including wire crossover problems and the added electrical inductances of the wires. Using pressure to inject the underfill material between the chip and the substrate, the amount of time required to dispense the underfill material would be reduced. The number of voids present in the underfill material would also be reduced, resulting in an increase in the reliabilities of the C4 solder ball connections.